IBM nanostack: 100B-transistor chip, 0.7nm node and gains

IBM has built a prototype chip with around 100 billion transistors on an area the size of a fingernail, and announced the design on Thursday as a path to denser, more efficient chips. The company says this density is twice that of its previous state-of-the-art technology from 2021 and that chips using the approach can do as much as 50% more work in the same time while being up to 70% more energy efficient.

What did IBM actually build?

IBM created a two-tier chip architecture it calls a nanostack, vertically stacking transistors in two layers on a silicon chip and combining two types of transistors into a complementary field-effect transistor, or CFET. Engineers fabricate transistors on one silicon layer, place another silicon layer on top, build transistors on that second layer, and then create electrical connections between the two layers; IBM says its second layer is staggered relative to the first, which simplifies wiring and offers other advantages.

The design follows a naming convention IBM uses, calling the technology “sub-nanometer” or “0.7 nanometer,” a marketing label rather than a literal physical measure. The company also notes the channel in its nanostack consists of three nanosheets that are each 15 atoms thick and spaced nine nanometers apart.

How does nanostacking differ from other two-tier approaches?

Nanostacking fabricates the second transistor layer directly on top of the first rather than bonding two independently fabricated layers together, and IBM says the staggered placement of its second layer eases wiring. Other two-tier methods such as AMD’s 3D V-Cache and Huawei’s LogicFolding bond separately made layers; IBM’s process allows tighter alignment across layers, which matters because transistors remain extremely small.

Big chipmakers including Intel, Samsung, and TSMC, and research lab Imec have been investigating CFETs, but IBM emphasizes its demonstration on a full wafer using a state-of-the-art manufacturing line and the staggered-stack distinction. IBM also expects designers will use the layout across many chip types, including GPUs and CPUs.

Why it matters

IBM’s nanostack targets density gains after device shrinkage hit physical limits: rather than pushing transistors to smaller geometries, the design builds up. Industry sources in the announcement framed this as a significant roadmap extension: Jay Gambetta, director of IBM Research, said, “It's not just an incremental step.” Dan Hutcheson, vice chair of TechInsights, added, “Absolutely, it’s transformational,” and suggested the technique could add ten to fifteen years to the roadmap. If adopted, the architecture could let data centers get more work per watt and better manage energy use.

The approach brings concrete performance claims: IBM reports up to 50% more work in the same time and up to 70% better energy efficiency compared with its prior generation. Those gains make the concept notable because conventional feature-size scaling has slowed; the industry has seen transistor pitch stay near about 40 nanometers even as generation names shrink.

What are the production challenges?

Stacking layers raises yield risk and thermal constraints. Fabrication errors in either layer can render a stacked chip defective, increasing cost compared with single-layer chips. Engineers also face a “thermal budget” problem: manufacturing steps must avoid melting connections to the layer underneath, effectively keeping processes below 400°C. IBM says it managed low enough temperatures to build the second stack but has not disclosed its methods.

Academic groups are exploring alternative low-temperature routes. Qing Cao’s group demonstrated a stacking method using processing below 200°C by employing junctionless transistors that avoid a high-temperature doping step. Cao described IBM’s work as transformative partly because it shows stacking on a full wafer in a modern fab, while also noting practical scale-up questions remain.

What to watch

Look for who IBM partners with and when manufacturers begin trial runs: IBM says it will partner with semiconductor manufacturers and expects many conversations with designers about using the technology. Also watch for public demonstrations of multi-tier yields and disclosed manufacturing temperatures or process steps, which will show whether nanostacking can scale beyond prototype wafers and into data-center deployments within the next decade as IBM suggests.