IBM sub-1 nanometer nanostack: 0.7 nm chip packs 100B transistors

IBM unveiled a new chip architecture that integrates nearly 100 billion transistors on a die the size of a human fingernail, a design the company calls the "world's first sub-1 nanometer chip technology." The architecture, which IBM describes as built at the 0.7-nanometer node and named the 7 angstrom node, was introduced at the 2025 IEEE Symposium on VLSI Technology and Circuits in Kyoto.

How does the nanostack architecture work?

The nanostack packs more transistors into the same area by vertically stacking transistors in a staggered layout, with the basic unit consisting of two transistors bonded together. Each transistor in that stack contains three nanosheets that are individually 5 nanometers thick, which IBM equates to about 15 rows of silicon atoms, and there is about 9 nanometers of separation between each nanosheet.

IBM builds the nanostack on its prior work with nanosheet transistors that underpinned the 2-nanometer node introduced in 2021. The vertical, staggered stacking departs from planar scaling and aims to deliver the effective density and performance one would expect from a hypothetical sub-1 nanometer physical process without making transistor features themselves smaller than fundamental physical limits allow.

What performance and memory gains does IBM claim?

IBM projects up to 50 percent higher computing performance or 70 percent greater energy efficiency versus its prior 2-nanometer node chips, based on the company’s published technical reports. Researchers also demonstrated a 40 percent improvement in SRAM scaling at the VLSI 2026 symposium, achieved by a staggered-channel design for six-transistor SRAM bit cells that reduces overall cell height by 40 percent and allows more SRAM in the same area.

Those memory gains matter because SRAM scaling has slowed in recent generations; Jay Gambetta, director of IBM Research and IBM Fellow, noted SRAM improved only a few percent between the 3-nanometer and 2-nanometer generations. Gambetta called the nanostack "not just an incremental step, it's a meaningful leap forward." The company positions these improvements specifically for AI workloads that demand higher bandwidth and efficiency.

Who will make these chips and what is the timeline?

IBM conducts chip technology research but does not manufacture commercial chips itself. For its 2-nanometer nanosheet work, IBM partnered with foundries such as Rapidus in Japan and worked with Samsung on related commercialization efforts, while other companies like TSMC independently developed nanosheet transistors for their own 2-nanometer processes. IBM did not name partners for commercializing the new sub-1-nanometer nanostack.

Huiming Bu, vice president of IBM Semiconductors Global R&D and IBM Research, said that commercial chips using the sub-1-nanometer node and the nanostack architecture could begin production "as early as in the next five years and most likely within a decade." Bu also said nanosheet has become the foundation for leading foundries' next-generation processes and expects nanostack to replace nanosheet as mainstream in those foundries.

Why it matters

The nanostack aims to address a core bottleneck for AI hardware: how to keep increasing compute and on-chip memory density without relying on ever-smaller physical transistor features. If the projected 50 percent performance gains or 70 percent energy improvements are realized in commercial chips, AI data centers could host denser, more power-efficient accelerators. The 40 percent SRAM scaling improvement directly addresses a feature that has lagged behind logic scaling and is critical for AI workloads that rely on fast, on-chip memory.

What to watch

Watch for foundry partnerships and early process integrations: IBM declined to name commercialization partners for the nanostack, and the first commercial production windows IBM suggested range from "as early as in the next five years" to "within a decade." Also monitor whether the projected 50 percent compute or 70 percent energy gains appear in foundry test chips and in how vendors adapt the staggered SRAM bit cell into AI accelerators.